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Freescale Semiconductor /MK20F12 /SIM /SCGC6

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Interpret as SCGC6

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (0)DMAMUX0 0 (0)DMAMUX1 0 (0)FLEXCAN0 0 (0)DSPI0 0 (0)DSPI1 0 (0)SAI0 0 (0)CRC 0 (0)USBHS 0 (0)USBDCD 0 (0)PDB 0 (0)PIT 0 (0)FTM0 0 (0)FTM1 0 (0)ADC0 0 (0)ADC2 0 (0)RTC

PDB=0, FLEXCAN0=0, USBDCD=0, FTM0=0, DMAMUX1=0, DMAMUX0=0, USBHS=0, RTC=0, FTM1=0, SAI0=0, CRC=0, DSPI0=0, ADC0=0, ADC2=0, DSPI1=0, PIT=0

Description

System Clock Gating Control Register 6

Fields

DMAMUX0

DMAMUX0 clock gate control

0 (0): Clock is disabled.

1 (1): Clock is enabled.
DMAMUX1

DMAMUX1 clock gate control

0 (0): Clock is disabled.

1 (1): Clock is enabled.
FLEXCAN0

FlexCAN0 clock gate control

0 (0): Clock is disabled.

1 (1): Clock is enabled.
DSPI0

DSPI0 clock gate control

0 (0): Clock is disabled.

1 (1): Clock is enabled.
DSPI1

DSPI1 clock gate control

0 (0): Clock is disabled.

1 (1): Clock is enabled.
SAI0

SAI0 clock gate control

0 (0): Clock is disabled.

1 (1): Clock is enabled.
CRC

CRC clock gate control

0 (0): Clock is disabled.

1 (1): Clock is enabled.
USBHS

USBHS clock gate control

0 (0): Clock is disabled.

1 (1): Clock is enabled.
USBDCD

USB DCD clock gate control

0 (0): Clock is disabled.

1 (1): Clock is enabled.
PDB

PDB clock gate control

0 (0): Clock is disabled.

1 (1): Clock is enabled.
PIT

PIT clock gate control

0 (0): Clock is disabled.

1 (1): Clock is enabled.
FTM0

FTM0 clock gate control

0 (0): Clock is disabled.

1 (1): Clock is enabled.
FTM1

FTM1 clock gate control

0 (0): Clock is disabled.

1 (1): Clock is enabled.
ADC0

ADC0 clock gate control

0 (0): Clock is disabled.

1 (1): Clock is enabled.
ADC2

ADC2 clock gate control

0 (0): Clock is disabled.

1 (1): Clock is enabled.
RTC

RTC clock gate control

0 (0): Clock is disabled.

1 (1): Clock is enabled.

Links

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Register License

Redistribution and use in source and binary forms, with or without modification,\nare permitted provided that the following conditions are met:\n o Redistributions of source code must retain the above copyright notice, this list\n of conditions and the following disclaimer.\n o Redistributions in binary form must reproduce the above copyright notice, this\n list of conditions and the following disclaimer in the documentation and/or\n other materials provided with the distribution.\n o Neither the name of Freescale Semiconductor, Inc. nor the names of its\n contributors may be used to endorse or promote products derived from this\n software without specific prior written permission.\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS “AS IS” AND\n ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR\n ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON\n ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data